The daily lives of young professionals can be thought of as a balancing act, as they struggle with juggling their different work and nonwork roles (Allen et al., 2019). Young professionals do not only invest a considerable amount of time and energy resources in starting their careers, but also in building up a family life. As such, many want to succeed as hard-working, devoted professionals (i.e., the ‘ideal worker’), as well as become, or come across as, involved and nurturing parents (i.e., the ‘ideal parent’) (Ladge & Little, 2018). In addition, young professionals tend to increasingly experience that they need to live up to perceived expectations coming from social network sites on how to showcase oneself in the most perfect way (i.e., the media ‘ideal’) (Shah & Tewari, 2016). Accordingly, young professionals may (re)construct ‘ideal’ images of themselves in the work, private, and online domains which lean towards these ideal selves and away from their undesired selves (Leary & Kowalski, 1990). In the context of the Conservation of Resources (COR) theory (Hobfoll & Wells, 1998), such an image (re)construction process (Dumas & Sanchez-Burks, 2015; Humberd et al., 2015; Roberts, 2005) may play a critical role in the attainment of relevant personal resources, such as pride, status and liking, on the one hand, and the loss of resources (i.e., energy resources), on the other hand.
Neighborhood image processing operations on Field Programmable Gate Array (FPGA) are considered as memory intensive operations. A large memory bandwidth is required to transfer the required pixel data from external memory to the processing unit. On-chip image buffers are employed to reduce this data transfer rate. Conventional image buffers, implemented either by using FPGA logic resources or embedded memories are resource inefficient. They exhaust the limited FPGA resources quickly. Consequently, hardware implementation of neighborhood operations becomes expensive, and integrating them in resource constrained devices becomes unfeasible. This paper presents a resource efficient FPGA based on-chip buffer architecture. The proposed architecture utilizes full capacity of a single Xilinx BlockRAM (BRAM36 primitive) for storing multiple rows of input image. To get multiple pixels/clock in a user defined scan order, an efficient duty-cycle based memory accessing technique is coupled with a customized addressing circuitry. This accessing technique exploits switching capabilities of BRAM to read 4 pixels in a single clock cycle without degrading system frequency. The addressing circuitry provides multiple pixels/clock in any user defined scan order to implement a wide range of neighborhood operations. With the saving of 83% BRAM resources, the buffer architecture operates at 278 MHz on Xilinx Artix-7 FPGA with an efficiency of 1.3 clock/pixel. It is thus capable to fulfill real time image processing requirements for HD image resolution (1080 × 1920) @103 fcps.
